Conventional high-speed analog-to-digital converters ("ADCs") commonly employ a full flash architecture in which the analog-to-digital conversion is done in parallel by using approximately 2.sup.n voltage comparators. FIG. 1 illustrates a conventional full flash ADC 100 including an input voltage 110, a reference voltage 112, a number of resistors, of which resistor 114 is representative, a number of conventional comparators, of which comparator 116 is representative, and a conventional decoder 118 that produces a multi-bit digital output 120.
As is well known in the art, input voltage 110 is applied simultaneously to each comparator 116. In addition, fractional portions of the reference voltage 112 are applied to the comparators 116 by dividing the reference voltage 112 in equal increments (or thresholds) by the resistors 114. The output of each comparator 116 is applied to the decoder 118 which decodes such received inputs into a multi-bit digital output 120 representative of the input voltage 110. Although a single-ended structure is shown in FIG. 1 and throughout this discussion, in practice a fully differential structure can be used.
ADCs for operation at high frequencies, however, require a large amount of integrated circuit area and have high power consumption, and all such requirements increase as the number of bit of resolution of the ADC increases. For example, a 6-bit full flash ADC requires about 2.sup.6 =64 voltage comparators. In a CMOS implementation of a full flash ADC, these comparators are normally implemented using conventional auto-zero voltage comparators. An auto-zero voltage comparator, however, requires a two-phase clock for auto-zeroing in the first phase, and for actual signal comparison in the second phase. Unfortunately, such two-phase design limits the maximum achievable operating frequency to a factor of two lower than otherwise possible, other factors being equal, if non-auto zero voltage comparators are employed.
Non-auto zero voltage comparators, such as those used in full flash ADCs implemented in Bipolar or BiCMOS integrated circuit processes, are generally not practical for implementation in standard CMOS processes because device mismatches (e.g., input offset voltage) of CMOS voltage comparators tend to be much higher than for Bipolar equivalents. CMOS voltage comparators with low input offset voltage can usually only be obtained using complex circuitry that requires large integrated circuit area with associated higher power consumption, and generally lower conversion speed.
Therefore, it is desirable to provide a high resolution ADC that has small die size and low power consumption, and that avoids the effects of operational mismatches.